My previous blog post covered the SEGGER Linker for RISC-V and the benefits provided by enhanced relaxation. This article continues to explore what SEGGER is doing with its linker technology, advancing what is typically possible.
Posts in the RISC-V category:
Code size: Closing the gap between RISC-V and Arm for embedded applications
One of the issues faced by RISC-V developers is that the code density of the RISC-V instruction set for deeply embedded processors does not match that of Cortex-M with existing tools. That is changing with the product innovations SEGGER have developed, such as the recently-announced SEGGER Linker, capable of reducing code size by up to […]
Profiling and Code coverage on RISC-V using simulation
We recently licensed our Floating point library for RISC-V to a large international corporation. They asked not only for our functional verification suite, but also for a verification of the verification suite. A code coverage report showing that the entire code had been executed. While we know that all lines and every instruction have been […]
RISC-V adoption and 7th Workshop thoughts
You have probably seen that SEGGER attended the recent (7th) RISC-V Workshop. There we demonstrated J-Link support for RISC-V cores and Embedded Studio for RISC-V, our professional-grade IDE that (unsurprisingly) targets RISC-V processors. This post offers a personal view on RISC-V and a reflection on the workshop.
